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| -1 - NJU6673 ver.2003-04-08 25-common x 100-segment bitmap lcd driver general description the NJU6673 is a 25-common x 100-segment bit map lcd driver to display graphics or characters. it contains 2,500 bits display data ram, microprocessor interface circuits, instruction decoder, and common and segment drivers. an image data from mpu through the serial or 8-bit parallel interface are stored into the 2,500 bits internal displayed on the lcd panel through the commons and segments drivers. the NJU6673 displays 25 x 100 dots graphics or 7-character 2-line by 12 x 13 dots character. the NJU6673 contains a built-in osc circuit for reducing external components. and it features an electrical variable resistor. as result, it reduces the operating current. the operating voltage from 2.4v to 5.5v and low operating current are suitable for small size battery operation items. features direct correspondence of display data ram to lcd pixel display data ram 2,500 bits lcd drivers 25-common and 100-segment selectable duty and bias ratio ; 1/25 duty 1/6 bias or 1/15 duty 1/5 bias direct connection to 8-bit microprocessor interface for both of 68 and 80 type mpu serial interface (si, scl, a0, cs) useful instruction set display on/off, display start line set, page address set, column address set, status read, write display data, read display data, normal or inverse on/off set, static drive on/normal display, evr register set, read modify write, end, reset, internal power supply on/off, driver output on/off, power save and adc select. power supply circuits for lcd; available attractive operation for small lcd panel without external capacitors for bias stabilization. booster circuits(3 times maximum, voltage boosting polarity : negative (v dd common)), regulator, voltage follower(x 4) precision electrical variable resistance (16 steps) low power consumption operating voltage 2.4v to 5.5v lcd driving voltage 4.0v to 10.0v package outline bumped chip c-mos technology (substrate : n) package outline NJU6673cl
- 2 - NJU6673 ver.2003-04-08 pad location chip center : x=0 m, y=0 m chip size : x=7.54mm, y=2.09mm chip thickness : 400 m 30 m bump size : 78.16 m x 48.10 m pad pitch : 70 m(min.) bump height : 15 m(typ.) bump material : au voltage boosting polarity : negative voltage(v dd common) substrate : n s 0 s 1 s 98 s 99 c 1 c 0 x y c 13 c 15 c 24 c 23 dummy 17 a li_b1 a li_b2 a li_a1 a li_a2 dummy 13 dummy 14 dummy 15 dummy 16 dummy 18 a 0 cs osc t 1 t 2 v ss sel68 p/s v dd res v ss v ss v dd v dd vr v dd v out c 2 - c 2 + duty rd wr cdir dummy 3 dummy 6 dummy 5 dummy 4 dummy 1 dummy 2 dummy 7 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 v ss v ss v ss c 1 - c 1 + c 1 - c 1 + c 1 - c 1 + c 2 - c 2 + c 2 - c 2 + v dd v out v dd v out dummy 12 vr dummy 10 v 5 dummy 11 vr v 4 v 3 v 2 v 5 v 4 v 5 v 4 v 3 v 2 v 1 v 3 v 2 v 1 v 1 dummy 8 dummy 9 c 14 -3 - NJU6673 ver.2003-04-08 terminal description chip size 7.54x2.09mm(chip center x=0 m, y=0 m) pad no. terminal x= m y= m pad no. terminal x= m y= m 1 dummy 1 -3536 -891 51 v out 1715 -891 2 dummy 2 -3466 -891 52 v out 1786 -891 3 res -3396 -891 53 v out 1856 -891 4 v dd -3326 -891 54 v dd 1926 -891 5 v dd -3256 -891 55 v dd 1996 -891 6 v dd -3186 -891 56 v dd 2066 -891 7 p/s -3116 -891 57 dummy 10 2136 -891 8 sel68 -3046 -891 58 vr 2206 -891 9 v ss -2976 -891 59 vr 2276 -891 10 v ss -2906 -891 60 vr 2346 -891 11 v ss -2836 -891 61 v 5 2416 -891 12 t2 -2766 -891 62 v 5 2486 -891 13 t1 -2696 -891 63 v 5 2556 -891 14 osc 1 -2626 -891 64 v 4 2626 -891 15 cs -2556 -891 65 v 4 2696 -891 16 a0 -2486 -891 66 v 4 2766 -891 17 wr -2416 -891 67 v 3 2836 -891 18 rd -2346 -891 68 v 3 2906 -891 19 duty -2276 -891 69 v 3 2976 -891 20 cdir -2206 -891 70 v 2 3046 -891 21 dummy 3 -2136 -891 71 v 2 3116 -891 22 dummy 4 -2066 -891 72 v 2 3186 -891 23 dummy 5 -1996 -891 73 v 1 3256 -891 24 dummy 6 -1926 -891 74 v 1 3326 -891 25 d 0 -1715 -891 75 v 1 3396 -891 26 d 1 -1435 -891 76 dummy 11 3466 -891 27 d 2 -1155 -891 77 dummy 12 3536 -891 28 d 3 -875 -891 78 ali_a2 3616 -891 29 d 4 -595 -891 79 dummy 13 3616 -745 30 d 5 -315 -891 80 dummy 14 3616 -675 31 d 6 (scl) -35 -891 81 c 0 3616 -605 32 d 7 (si) 245 -891 82 c 1 3616 -535 33 dummy 7 455 -891 83 c 2 3616 -465 34 v ss 525 -891 84 c 3 3616 -395 35 v ss 595 -891 85 c 4 3616 -325 36 v ss 665 -891 86 c 5 3616 -255 37 dummy 8 735 -891 87 c 6 3616 -185 38 dummy 9 805 -891 88 c 7 3616 -115 39 c1 + 875 -891 89 c 8 3616 -45 40 c1 + 945 -891 90 c 9 3616 25 41 c1 + 1015 -891 91 c 10 3616 95 42 c1 - 1085 -891 92 c 11 3616 166 43 c1 - 1155 -891 93 c 12 3616 236 44 c1 - 1225 -891 94 c 13 3616 306 45 c2 + 1295 -891 95 c 14 3616 376 46 c2 + 1365 -891 96 ali_b1 3616 873 47 c2 + 1435 -891 97 dummy 15 3536 891 48 c2 - 1505 -891 98 s 0 3466 891 49 c2 - 1575 -891 99 s 1 3396 891 50 c2 - 1645 -891 100 s 2 3326 891 - 4 - NJU6673 ver.2003-04-08 pad no. terminal x= m y= m pad no. terminal x= m y= m 101 s 3 3256 891 151 s 53 -245 891 102 s 4 3186 891 152 s 54 -315 891 103 s 5 3116 891 153 s 55 -385 891 104 s 6 3046 891 154 s 56 -455 891 105 s 7 2976 891 155 s 57 -525 891 106 s 8 2906 891 156 s 58 -595 891 107 s 9 2836 891 157 s 59 -665 891 108 s 10 2766 891 158 s 60 -735 891 109 s 11 2696 891 159 s 61 -805 891 110 s 12 2626 891 160 s 62 -875 891 111 s 13 2556 891 161 s 63 -945 891 112 s 14 2486 891 162 s 64 -1015 891 113 s 15 2416 891 163 s 65 -1085 891 114 s 16 2346 891 164 s 66 -1155 891 115 s 17 2276 891 165 s 67 -1225 891 116 s 18 2206 891 166 s 68 -1295 891 117 s 19 2136 891 167 s 69 -1365 891 118 s 20 2066 891 168 s 70 -1435 891 119 s 21 1996 891 169 s 71 -1505 891 120 s 22 1926 891 170 s 72 -1575 891 121 s 23 1856 891 171 s 73 -1645 891 122 s 24 1786 891 172 s 74 -1715 891 123 s 25 1715 891 173 s 75 -1786 891 124 s 26 1645 891 174 s 76 -1856 891 125 s 27 1575 891 175 s 77 -1926 891 126 s 28 1505 891 176 s 78 -1996 891 127 s 29 1435 891 177 s 79 -2066 891 128 s 30 1365 891 178 s 80 -2136 891 129 s 31 1295 891 179 s 81 -2206 891 130 s 32 1225 891 180 s 82 -2276 891 131 s 33 1155 891 181 s 83 -2346 891 132 s 34 1085 891 182 s 84 -2416 891 133 s 35 1015 891 183 s 85 -2486 891 134 s 36 945 891 184 s 86 -2556 891 135 s 37 875 891 185 s 87 -2626 891 136 s 38 805 891 186 s 88 -2696 891 137 s 39 735 891 187 s 89 -2766 891 138 s 40 665 891 188 s 90 -2836 891 139 s 41 595 891 189 s 91 -2906 891 140 s 42 525 891 190 s 92 -2976 891 141 s 43 455 891 191 s 93 -3046 891 142 s 44 385 891 192 s 94 -3116 891 143 s 45 315 891 193 s 95 -3186 891 144 s 46 245 891 194 s 96 -3256 891 145 s 47 175 891 195 s 97 -3326 891 146 s 48 105 891 196 s 98 -3396 891 147 s 49 35 891 197 s 99 -3466 891 148 s 50 -35 891 198 dummy 16 -3536 891 149 s 51 -105 891 199 ali_b2 -3616 873 150 s 52 -175 891 200 c 24 -3616 25 -5 - NJU6673 ver.2003-04-08 pad no. terminal x= m y= m 201 c 23 -3616 -45 202 c 22 -3616 -115 203 c 21 -3616 -185 204 c 20 -3616 -255 205 c 19 -3616 -325 206 c 18 -3616 -395 207 c 17 -3616 -465 208 c 16 -3616 -535 209 c 15 -3616 -605 210 dummy 17 -3616 -675 211 dummy 18 -3616 -745 212 ali_a1 -3616 -891 ? alignment marks note) alignment marks are not contains window. 110.34 - 6 - NJU6673 ver.2003-04-08 block diagram dut y internal bus com driver shift register c 24 c 15 s 99 s 0 seg driver dis p la y data latch 100 display data ram 100 x 25 bit row address decoder line address decoder column address decoder line counter column address counter 8bi t column address re g ister 8bi t multi p lexer page address register v ss v dd 5 v 1 to v 5 com, seg timing generator display timing generator osc. i/o buffer output assignment register status bf bus holder instruction decoder reset res cpu interface sel68 p/s a 0 wr rd d 0 to d 5 d 6 (scl) d 7 (si) osc voltage generator c 1 + c 1 - c 2 + c 2 - vr cs com driver shift register c 0 c 14 t 1 t 2 cdir start line register -7 - NJU6673 ver.2003-04-08 terminal description no. symbol i/o function 1, 2, 21- 24, 33, 37, 38, 57, 76, 77, 79, 80, 97, 198, 210, 211 dummy 1 dummy 2 dummy 3 - dummy 6 dummy 7 dummy 8 dummy 9 dummy 10 dummy 11 dummy 12 dummy 13 dummy 14 dummy 15 dummy 16 dummy 17 dummy 18 dummy terminal. these are open terminals electrically. 4,5,6, 54-56 v dd power power supply terminal. (+2.4 to +5.5v) 9-11, 34-36 v ss gnd ground terminal. (0v) lcd driving voltage supplying terminals. in case of external power supply operation without internal power supply operation, each level of lcd driving voltage is supplied from outside fitting with following relation. v dd v 1 v 2 v 3 v 4 v 5 v out in case of internal power supply, lcd driving voltages v 1 to v 4 depending on the bias selection are supplied as shown in follows; duty bias v 1 v 2 v 3 v 4 1/15 duty 1/5 bias v 5 +4/5 v lcd v 5 +3/5 v lcd v 5 +2/5 v lcd v 5 +1/5 v lcd 1/25 duty 1/6 bias v 5 +5/6 v lcd v 5 +4/6 v lcd v 5 +2/6 v lcd v 5 +1/6 v lcd 73-75 70-72 67-69 64-66 61-63 v 1 v 2 v 3 v 4 v 5 power v lcd =v dd -v 5 39-41 42-44 45-47 48-50 c 1 + c 1 - c 2 + c 2 - o condenser connecting terminals for internal voltage booster. boosting time is selected by each connected condenser. in case of 3-time boost operation, connect the condenser between c 1 + and c 1 -, c 2 + and c 2 -. in case of 2-time boost operation, connect the condenser between c 2 + and c 2 -, connect c 2 + to c 1 +, and c 1 - should be open. 51-53 v out o boosted voltage output terminal. connects the capacitor between v out terminal and v ss . 58-60 vr i v lcd voltage adjustment terminal. the gain of v lcd setup circuit for v 5 level is adjusted by external resistor. lcd bias voltage control terminals. t 1 t 2 voltage booster circuit voltage adjustor v/f circuit l h/l available available available h l not available available available h h not available not available available 13 12 t 1 , t 2 i 25 26 27 28 29 30 31 32 d 0 d 1 d 2 d 3 d 4 d 5 d 6 (scl) d 7 (si) i/o data input / output terminals. in parallel interface mode (p/s=?h?) i/o terminals of 8-bit bus. in serial interface mode(p/s=?l?) d 7 :input terminal of serial data (si). d 6 :input terminal of serial data clock (scl). d 5 to d 0 terminals are high impedance. when cs=?h? , d 0 to d 7 terminals are high-impedance. - 8 - NJU6673 ver.2003-04-08 no. symbol i/o function data discremination signal input terminal. the signal from mpu discreminates transmitted data between display data and instruction. a0 h l discremination display data instruction 16 a0 i 3 res i reset terminal. reset operation is executing during ?l? state of res. 15 cs i chip select signal input terminal. data input/output are available during cs ="l". 18 rd (e) i rd(80 type) or e(68 type) signal input terminal. -9 - NJU6673 ver.2003-04-08 no. symbol i/o function lcd driving signal output terminals. common output terminals :c 0 to c 24 segment output terminals :s 0 to s 99 ? common output terminal following output voltages is selected by the combination of alternating(fr) signal and common scanning data. 81-95 c 0 -c 14 o scan data fr output voltage h v 5 h l v dd h v 1 l l v 4 98-197 s 0 -s 99 o ? segment output terminal following output voltages is selected by the combination of alternating(fr) signal and display data in the dd ram. output voltage ram data fr normal reverse h v dd v 2 h l v 5 v 3 h v 2 v dd l l v 3 v 5 200-209 c 24 -c 15 o duty and bias selection terminal. duty duty bias h 1/15 1/5 l 1/25 1/6 19 duty i common driver assignment selection terminal. cdir common output terminals h reverse (c 24 c 0 ) l normal (c 0 c 24 ) 20 cdir i - 10 - NJU6673 ver.2003-04-08 functional description (1) description for each blocks (1-1) busy flag (bf) the busy flag (bf) is set to logical ?1? in busy of internal execution by an instruction, and any instruction excepting for the ?status read? is disable at this time. busy flag is outputted through d 7 terminal by ?status read? instruction. although another instructions should be inputted after check of busy flag, no need to check busy flag if the system cycle time (t cyc ) as shown in bus timing characteristics is secured completely. (1-2) display start line register the display start line register is a register to set a display data ram address corresponding to the com 0 display line (the top line normally) for the vertical scroll on the lcd, page address change and so forth. the display start line address set instruction sets the 8-bit display start address into this register. (1-3) line counter line counter is reset when the internal fr signal is switched and outputs the line address of the display data ram by count up operation synchronizing with common cycle of NJU6673 . (1-4) column address counter column address counter is the 8-bit preset-able counter to point the column address of the display data ram (dd ram) as shown in fig. 1. the counter is incremented automatically after the display data read/write instructions execution. when the column address counter reaches to the maximum existing address by the increment operations, the count up operation (increment) is frozen. however, when new address is set to the column address counter again, it restarts the count up operation from a set address. the operation of column address counter is independent against page address register. by the address inverse instruction (adc select) as shown in fig. 1, column address decoder reverses the correspondence between column address and segment output of display data ram. (1-5) page address register page address register assigns the page address of the display data ram as shown in fig. 1. in case of accessing from the mpu with changing the page address, page address set instruction is required. (1-6) display data ram the display data ram (dd ram) is the bit map ram consisting of 2,500 bits to store the display data corresponding to the lcd pixel on lcd panel. in normal display : ?1? turn-on display, ?0?=turn-off display in reveres display : ?1? turn-off display, ?0?=turn-on display dd ram output 100 bits parallel data addressed by line address counter then the data latched in the display data latch. asynchronous data access to the dd ram is available due to the access to the dd ram from the mpu and latch to the display data latch operation are done independently. (1-7) common driver assignment the scanning order can be assigned by set common driver assignment selection terminal as shown on table 1. table 1 common driver order assignment com outputs terminals pad no. 81 95 200 209 pin name c 0 c 14 c 24 c 15 ?l? com 0 com 14 com 24 com 15 com driver assignment selection terminal ?h? com 24 com 10 com 0 com 9 the duty ratio setting and output assignment register are so controlled to operate independently that duty ratio setting required to corresponding duty ratio for output assignment. - 11 - NJU6673 ver.2003-04-08 page address data display pattern line address com output example 1 d 0 00 c 17 d 1 01 c 18 d 2 02 c 19 d 3 03 c 20 d 4 04 c 21 d 5 05 c 22 d 6 06 c 23 d 1 , d 0 (0, 0) d 7 page 0 07 c 24 com output example 2 d 0 08 c 0 c 0 d 1 09 c 1 c 1 d 2 0a c 2 c 2 d 3 0b c 3 c 3 d 4 0c c 4 c 4 d 5 0d c 5 c 5 d 6 0e c 6 c 6 d 1 , d 0 (0, 1) d 7 page 1 0f c 7 c 7 d 0 10 c 8 c 8 d 1 11 c 9 c 9 d 2 12 c 10 c 10 d 3 13 c 11 c 11 d 4 14 c 12 c 12 d 5 15 c 13 c 13 d 6 16 c 14 c 14 d 1 , d 0 (1, 0) d 7 page 2 17 c 15 d 1 , d 0 (1, 1) d 0 page 3 18 c 16 d 0 =0 00 01 02 03 04 05 62 63 column address(adc) d 0 =1 63 62 61 60 5f 5e 01 00 segment output s 0 s 1 s 2 s 3 s 4 s 5 s 98 s 99 com output example1 : 1/25duty, set display start line 08 h com output example2 : 1/15duty, set display start line 08 h fig.1 correspondence with display data ram address - 12 - NJU6673 ver.2003-04-08 (1-8) reset circuit reset circuit operates the following initializations when the condition of res terminal goes to "l" level. ? initialization 1. display off 2. normal display (non-inverse display) 3. adc select : normal (adc instruction d 0 =?0?) 4. read modify write mode off 5. voltage booster off, voltage regulator off, voltage follower off 6. clear the serial interface register 7. driver output off 8. set the display start line register to 00 h 9. set the column address counter to 00 h 10. set the page address register to page ?0? 11. set the evr register to 00 h the res terminal connects to the reset terminal of the mpu synchronization with the mpu initialization as shown in ?the mpu interface? in the application circuit section. the ?l? level input signal as reset signal must keep the period over than 10 s as shown in dc characteristics. the NJU6673 takes 1 s for the reset operation after the rising edge of the res signal. the reset operation by res =?l? initializes each resister setting as above reset status, but the internal oscillation circuit and output terminals (d 0 to d 7 ) are not affected. to avoid the lock-up, the reset operation by the res terminal must be required every time when power terns on. the reset operation by the reset instruction, function 8 to 11 operations mentioned above is performed. the res terminal must be keep ?l? level when the power terns on in not use of the built-in lcd power supply circuit for no affect to the internal execution. (1-9) lcd driving (a) lcd driving circuits lcd driver is 125 sets of multiplexer consisting of 100 segments and 25 commons drivers to output lcd driving voltage. the common driver outputs the common scan signals formed with the shift register. the segment driver outputs the segment driving signal determined by a combination of display data in the dd ram, common timing, fr signal, and alternating signal for lcd. the output wave forms of segment/common are shown in lcd driving waveform. (b) display data latch circuits display data latch circuit latches the 100 bits display data outputted from the dd ram addressed by the line address counter to lcd driver at every common signal cycle temporarily. the original data in the dd ram is not changed because of the normal/reverse display, display on/off, static drive on/off instruction processes only stored data in this display data latch circuit. (c) line counter and latch signal of latch circuits the count clock to line counter and the latch clock to display data latch circuit are formed using the internal display clock (cl). the display data of 100 bits from display data ram pointed by the line address synchronizing with the internal display clock are latched into the display data latch circuit and are outputted to lcd driving circuits. the display data read out operation from dd ram to the lcd driver circuit is completely independent operation with an access to the display data ram from mpu. - 13 - NJU6673 ver.2003-04-08 (d) display timing generaton circuit the display timing generation circuit generates the internal timing of the display system by the master clock and the internal fr signal. as for it, the internal fr signal and the lcd alternating signal generate the wave form of 2-frame alternating drive wave form or the n-line inverse drive method for the lcd driving circuit. (e) common timing generation the common timing generator generates the common timing signal from the display clock (cl). fig. .2 (f) oscillation circuit the oscillation circuit is a low power type cr oscillator using an internal resistor and capacitor. the oscillator output is using for the display timing clock and for the voltage booster circuit. and the display clock(cl) is generated from this oscillator output frequency by dividing. table 2 the relation between duty and divide duty 1/15 1/25 divide 1/10 1/6 cl fr c 0 c 1 ram data sn 24 25 1 2 3 4 5 6 7 8 23 24 25 1 2 3 4 5 6 7 v dd v dd v dd v 1 v 1 v 4 v 2 v 4 v 5 v 5 v 5 v 3 - 14 - NJU6673 ver.2003-04-08 (g) power supply circuit the internal power supply circuit generates the voltage for driving lcd. it consists of voltage booster circuits (3-time maximum), voltage regulator circuits, and voltage followers. the operation of internal power supply circuits is controlled by the internal power supply on/off instruction. when the internal power supply off instruction is executed, all of the voltage booster circuits, regulator circuits, voltage follower circuits are turned off. in this time, the bias voltage of v 1 , v 2 , v 3 , v 4 , v 5 and v out for the lcd should be supplied from outside, terminals c 1 +, c 1 -, c 2 +, c 2 - and vr should be open. the status of internal power supply is selected by t 1 and t 2 terminals. furthermore the external power supply operates with some of internal power supply function. table3 the relation between power supply circuit and t 1 , t 2 terminal t 1 t 2 voltage booster voltage adj. buffer(v/f) ext.power supply c 1 +, c 1 -, c 2 +, c 2 - vr term. l l/h on on on - h l off on on v out open h h off off on v 5 , v out open open when (t 1 , t 2 )=(h, l), c 1 +, c 1 -, c 2 +, c 2 - terminals for voltage booster circuits are open because the voltage booster circuits doesn't operate. therefore lcd driving voltage to the v out terminal should be supplied from outside. when (t 1 , t 2 )=(h, h), terminals for voltage booster circuits and vr are open, because the voltage booster circuits and voltage adjust circuits do not operate. the internal power supply circuits is designed specially for a small-size lcd like as normal cellular phone size lcd panel. when NJU6673 apply to the large size lcd panel application (large capacitive load), external power supply is required to keep good display condition. the external capacitors to v 1 to v 5 for bias voltage stabilization may be removed in use of small size lcd panel. the equivalent load of lcd panel may be changed depending on display patterns. therefore, it require display quality check on various display patterns actually without external capacitors. if the display quality is not so good, external capacitors should connects as show in (3-4)lcd driving voltage generation circuits -fig. 4. (if no need external capacitors as result of experiment, the application patterns (wiring) should be prepared for recovery.) - 15 - NJU6673 ver.2003-04-08 { { { { power supply applications (1) internal power supply example. (2) only v out supply from outside example. all of the internal booster, voltage regulator, internal voltage regulator, voltage follower using. voltage follower using internal power supply on (instruction) internal power supply on (instruction) (t 1 , t 2 )=(l, l) (t 1 , t 2 )=(h, l) (3) v out and v 5 supply from outside example. (4) external power supply example. internal voltage follower using. all of v 1 to v 5 and v out supply from outside internal power supply (instruction) internal power supply (instruction) (t 1 , t 2 )=(h, h) (t 1 , t 2 )=(h, h) : these switches should be open during the power save mode. v dd v out v 1 v 2 v 4 v 3 v 5 v ss NJU6673 + + + + + + t 1 t 2 v dd + + c 1 + c 1 - c 2 + c 2 - v 5 vr + + + + + v dd v out v 1 v 2 v 4 v 3 v 5 v ss NJU6673 t 1 t 2 v dd vr v 5 + + + + v dd v 1 v 3 v 5 v ss t 1 t 2 v 4 v out v 2 NJU6673 v dd v 1 v 3 v 5 v ss t 1 t 2 NJU6673 v 3 v 1 v out - 16 - NJU6673 ver.2003-04-08 (2) instruction the NJU6673 distinguishes the signal on the data bus d 0 to d 7 as an instruction by combination of a0 , rd and wr(r/w). the decode of the instruction and execution performs with only high speed internal timing without relation to the external clock. therefore no busy flag check required normally. in case of serial interface, the data input as msb(d 7 ) first serially. the table. 4 shows the instruction codes of the NJU6673 . table 4 instruction code (*:don't care) code instruction a0 rd wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 description (a) display on/off 0 1 0 1 0 1 0 1 1 1 0/1 lcd display on/off d 0 =0:off d 0 =1:on (b) display start line set 0 1 0 0 1 * start address determine the display line of ram to com 0 (c) page address set 0 1 0 1 0 1 1 * * page address set the page of dd ram to the page address register column address set high order 3bits 0 1 0 0 0 0 1 0 high order column set the higher order 3 bits column address to the reg. (d) column address set lower order 4bits 0 1 0 0 0 0 0 lower order column add set the lower order 4 bits column address to the reg. (e) status read 0 0 1 status 0 0 0 0 read out the internal status (f) write display data 1 1 0 write data write the data into the display data ram (g) read display data 1 0 1 read data read the data from the display data ram (h) normal or inverse of on/off set 0 1 0 1 0 1 0 0 1 1 0/1 inverse the on and off display (i) static drive on /normal display 0 1 0 1 0 1 0 0 1 0 0/1 whole display turns on d 0 =0: normal d 0 =1: whole disp. on (j) evr register set 0 1 0 1 0 0 0 setting data set the v 5 output level to the evr register (k) read modify write 0 1 0 1 1 1 0 0 0 0 0 increment the column address register when writing but no-change when reading (l) end 0 1 0 1 1 1 0 1 1 1 0 release from the read modify write mode (m) reset 0 1 0 1 1 1 0 0 0 1 0 initialize the internal circuits (n) internal power supply on/off 0 1 0 0 0 1 0 0 1 0 0/1 0:int. power supply off 1:int. power supply on (o) driver outputs on/off 0 1 0 1 0 1 0 1 0 1 0/1 d 0 =0: lcd driver outputs off d 0 =1: lcd driver outputs on (p) power save (complex command) 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 1 1 0 0 1 set the power save mode (lcd display off + static drive on) (q) adc select 0 1 0 1 0 1 0 0 0 0 0/1 set the dd ram vs segment d 0 =0 :normal d 0 = 1:inverse - 17 - NJU6673 ver.2003-04-08 (2-1) explanation of instruction code (a) display on/off it executes the on/off control of the whole display without relation to the dd ram or any internal conditions. a0 rd wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 1 0 1 0 1 1 1 d d 0: display off 1: display on (b) display start line it sets the dd ram line address corresponding to the com 0 terminal (normally assigned to the top display line). in this instruction execution, the display area is automatically set by the lines that correspond to the display duty ratio to the upward direction of the line address. changing the line address by this instruction performs smooth scrolling to a vertical direction. in this time, the dd ram data are unchanged. a0 rd wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 0 1 * a 4 a 3 a 2 a 1 a 0 a 4 a 3 a 2 a 1 a 0 line address(hex) 0 0 0 0 0 00 0 0 0 0 1 01 : : : : 1 1 0 0 0 18 (c) page address set when mpu accesses to the dd ram, a page address is set by page address set instruction before writing the data (note:the change of page address is not affected to the display). a0 rd wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 1 0 1 1 * * a 1 a 0 a 1 a 0 page 0 0 0 0 1 1 1 0 2 1 1 3 *:don?t care - 18 - NJU6673 ver.2003-04-08 (d) column address when mpu accesses to the dd ram, row address set by page address set instruction is required with the column address before writing the data. the column address set requires twice address set which are higher order 3 bits address set and lower order 4 bits. when the mpu accesses to the ddram continuously, the column address increments automatically from the set address after each data access. therefore, the mpu can transmit only the data continuously without setting the column address at every transmission time. the increment of the column address is stopped at the maximum column address plus 1 limited by each display mode. when the column address count up is stopped, the row address is not changed. a0 rd wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 0 0 0 1 0 a 6 a 5 a 4 higher order 0 1 0 0 0 0 0 a 3 a 2 a 1 a 0 lower order a 6 a 5 a 4 a 3 a 2 a 1 a 0 column address (hex) 0 0 0 0 0 0 0 00 0 0 0 0 0 0 1 01 : : : : 1 1 0 0 0 1 1 63 (e) status read this instruction reads out the internal status of "busy", "adc", "on/off" and "reset" as follows. a0 rd wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 0 1 busy adc on/off reset 0 0 0 0 busy:busy=1 indicate the operating or the reset cycle. the instruction can be input after the busy status change to "0". adc : indicate the output correspondence of column (segment) address and segment driver. 0: counterclockwise output (inverse) 1: clockwise output (normal) note) the data ?0=inverse? and ?1=normal? of adc status is inverted with the adc select instruction of "1=inverse" and "0=normal". on/off: indicate the whole display on/off status. 0: whole display "on? 1: whole display "off " note) the data "0=on" and "1=off" of display on/off status is inverted with the display on/off instruction data of "1=on" and "0=off". reset :indicate the initializing by res signal or reset instruction. 0: not reset status 1: in the reset status (f) write display data it writes the data on the data bus into the dd ram column address increments automatically after data writing, therefore, the mpu can write the data into the dd ram continuosly without the address setting at every writing time once the starting address is set. a0 rd wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 1 1 0 write data - 19 - NJU6673 ver.2003-04-08 (g) read display data this instruction reads out the 8-bit data from dd ram addressed by the column and the page address.the column address automatically increments after the 8-bit read out, therefore, the mpu can read the data from the dd ram continuously without the address setting at every reading time once the starting address is set. note that the dummy read is required just after setting the column address (see?(4-4)access to the dd ram and the internal register?). in the serial interface mode, the display data is unable to read out. a0 rd wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 1 0 1 read data (h) normal or inverse on/off set it changes the display condition of normal or reverse for entire display area. the execution of this instruction does not change the display data in the dd ram. a0 rd wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 1 0 1 0 0 1 1 d d 0: normal ram data ?1? correspond to ?on? 1: inverse ram data ?0? correspond to ?on? (i) static drive this instruction turns all the pixels on regardless the data stored in the dd ram. in this time, the data in dd ram are remained and unchanged. this instruction is executed prior to the ?normal or inverse on/off set? instruction. a0 rd wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 1 0 1 0 0 1 0 d d 0: normal display 1: whole display turns on (j) evr register set it controls the voltage regulator circuit of the internal lcd power supply to adjust the lcd display contrast by changing the lcd driving voltage ?v 5 ?. by data setting into the evr register, the lcd driving voltage ?v 5 ? selects out of 16 steps of regulated voltage. the voltage adjustable range of ?d 5 ? is fixed by the external resistors. for details, refer the section?(3-2) voltage adjust circuits?. a0 rd wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 1 0 0 0 a 3 a 2 a 1 a 0 a 3 a 2 a 1 a 0 v lcd 0 0 0 0 low : : : : 1 1 1 1 high v lcd =v dd -v 5 when evr doesn't use, set the evr register to (0,0,0,0). - 20 - NJU6673 ver.2003-04-08 (k) read modify write this instruction sets the read modify write controlling the page address increment. in this mode, the column address only increments when execute the display data ?write instruction; but no change when the display data ?read ? instruction. this status is continued until the end instruction execution. when the end instruction is executed, the column address goes back to the start address before the execution of this ?read modify write? instruction. this function reduces the load of mpu for repeating display data change of the fixed area (ex. cursor blink) a0 rd wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 1 1 1 0 0 0 0 0 note) in this ?read modify write? mode, out of display data ?read?/?write?, any instructions except ?column address set? can be executed. the example of read modify write sequence page address set column address set read modify write yes set to the start address of curs or displa y start to the read modify write dummy read data read data write end dummy read data read data write end the read modify write finish? no dummy read data read data write column counter doesn?t increase column counter increase the data is i g nored column counter doesn?t increase column counter doesn?t increase data inverse b y mpu column counter doesn?t increase column counter increase column counter doesn?t increase column counter doesn?t increase column counter increase - 21 - NJU6673 ver.2003-04-08 (l) end this instruction releases the read modify write mode and the column address back to the address where the read modify write mode setting. a0 rd wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 1 1 1 0 1 1 1 0 return column address n n+1 n+2 n+3 n+m n read modify write set end (m) reset this instruction executes the following initialization. the reset by the reset signal input to the res terminal (hardware reset) is required when power turns on. this reset instruction does not use instead of this hardware reset when power turns on. initialization 1) set the display start line register to 00 h . 2) set the column address counter to 00 h . 3) set the page page address register to page ?0?. 4) set the evr register to 0 h . the dd ram is not affected of this initialization. a0 rd wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 1 1 1 0 0 0 1 0 (n) internal power supply on/off this instruction control on and off for the internal voltage converter, voltage regulator and voltage follower circuits. for the booster circuits operation, the oscillation circuits must be in operation. a0 rd wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 0 0 1 0 0 1 0 d d 0: internal power supply off 1: internal power supply on the internal power supply must be off when external power supply using. *1 the set up period of internal power supply on depends on the step up capacitors, voltage stabilizer capacitors, v dd and v lcd . therefore it requires the actual evaluation using the lcd module to get the correct time.(refer to the (3-4) fig.4) - 22 - NJU6673 ver.2003-04-08 (o) driver outputs on/off this instruction controlls on/off of the lcd driver outputs. a0 rd wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 1 0 1 0 1 0 1 d d 0: lcd driving waveform output off 1: lcd driving waveform output on the NJU6673 implements low power lcd driving voltage generator circuit and requires the following power supply on/off sequence. lcd driving power supply on/off sequences the sequences below are required when the power supply turns on/off.for the power supply turning on operation after the power-save mode, refer the ?power save release sequence? mentioned after. *1 : the internal power supply rise time is depending on the condition of the supply voltage, v lcd =v dd -v 5 external capacitor of booster, and external capacitor connected to v 1 to v 5 . to know the rise time correctly, test by using the actual lcd module. (wait time) *1 internal power supply on or external power supply on turn on sequence turn off sequence driving outputs on e.v.r. register set internal power supply off or external power supply off NJU6673 power off display off whole display on (wait time) *1 - 23 - NJU6673 ver.2003-04-08 (p) power save(complex command) when static drive on at the display off status(inverse order also same), the internal circuits goes to the power save mode and the operating current is dramatically reduced, almost same as the standby current. the internal status in the power save mode is shown as follows; 1: the oscillation circuits and the internal power supply circuits stop the operation. 2: lcd driving is stopped. segment and common drivers output v dd level voltage. 3: the display data and the internal operating condition are remained and kept as just before enter the power save mode. 4: all the lcd driving bias voltage(v 1 to v 5 ) is fixed to the v dd level. the power save and its release perform according to the following sequences. the NJU6673 constantly spends the current without the execution of the driver outputs off instruction. the lcd drive waveform is not output until the driver outputs on instruction is executed. *1 : in the power save sequence, the power save mode starts after the static drive on bcommand is executed. *2 : in the power save release sequence, the power save mode releases just after the static drive off instruction execution. the display on instruction is allowed to execute at any time after the static drive off instruction is completed. *3 : the internal power supply rise time is depending on the condition of the supply voltage, v lcd =v dd -v 5 , external capacitor of booster, and external capacitor connected to v 1 to v 5 . to know the rise time correctry, test by using the actual lcd module. *4 : lcd driving waveform is output after the exection of the driver outputs on instruction execution. *5 : in case of the external power supply operation, the external power supply should be turned off before the power save mode and connected to the v dd for fixing the voltage of v out terminal. in this time, v out terminal also should be made codition like as disconection to the lowest voltage of the system. (q) adc select this instruction determines the correspondence of column in the dd ram with the segment driver outputs. segment driver outout order is inverse when this instruction executes, therefore, the placement the NJU6673 against the lcd panel becomes easy. a0 rd wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 1 0 1 0 0 0 0 0/1 d 0: clokwise output(normal) 1: counterclockwise output(inverse) static drive on { { { { power save sequence { { { { power save release sequence driver outputs off display off display on normal display driver outputs on (static drive on) (wait time) - 24 - NJU6673 ver.2003-04-08 (3) internal power supply (3-1) voltage tripler the 3-time voltage booster circuit outputs the negative voltage(v dd common) boosted 3 times of v dd -v ss from the v out terminal with connecting the five capacitors between c 1 + and c 1 -, c 2 + and c 2 -, and v ss and v out . in case of the 2-time voltage booster operation, connect the two capacitor between c 2 + and c 2 -, v ss and v out , then connect the c 1 + and c 2 + terminals. voltage booster circuits requires the clock signals from internal oscillation circuit or the external clock signal. therefore, the internal oscillation circuits or the external clock supplier must be operating when the voltage booster is in operation. the boosted voltage of v dd -v out must be 10v or less. the boost voltage and the capacitor connection are shown below. the boosted voltage and v dd , v ss 2 time voltage 3 time voltage (3-2) voltage adjust circuits the boosted voltage of v out outputs v 5 for lcd driving through the voltage adjust circuits. the output voltage of v 5 is adjusted by ra and rb within the range of |v 5 | < |v out |. the output is calculated by the following formula(1). v lcd = v dd -v 5 = (1+rb/ra)v reg (1) the v reg voltage is a reference voltage generated by the built-in bleeder registance. v reg is adjustable by evr functions (see section 3-3). for minor adjustment of v 5 , it is recommended that the ra and rb is composed of r 2 as variable resistor and r 1 and r 3 as fixed resistors, constant should be connected to v dd terminal,vr and v 5 ,as shown below. fig-3 voltage adjust circuit - 25 - NJU6673 ver.2003-04-08 (3-3) contrast adjustment by the evr function the evr selects the v reg voltage out of the following 16 conditions by setting 4-bit data into the evr register. with the evr function, v reg is controlled, and the lcd display contrast is adjusted. the evr controls the voltage of v reg by instruction and changes the voltage of v 5 . a step with evr is set like table shown below. evr register v reg [v] v lcd 0 h (0, 0, 0, 0) (135/150)(v dd -v ss ) low 1 h (0, 0, 0, 1) (136/150)(v dd -v ss ) : 2 h (0, 0, 1, 0) (137/150)(v dd -v ss ) : : : : : : : : : e h (1, 1, 1, 0) (149/150)(v dd -v ss ) : f h (1, 1, 1, 1) (150/150)(v dd -v ss ) high * in use of the evr function, the voltage adjustment circuit must turn on by the power supply instruction. adjustable range of the lcd driving voltage by evr function the adjustable range is decided by the power supply voltage v dd and the ratio of external resistors ra and rb. [ design example for the adjustable range / reference ] - condition v dd =3.0v, v ss =0v ra=1m ? , rb=1m ? ( ra:rb=1:1 ) the adjustable range and the step voltage are calculated as follows in the above condition. in case of setting 00 h in the evr register, v lcd = ((ra+rb)/ra) v reg = (2/1)[(135/150)3.0] = 5.4v in case of setting 0f h in the evr register, v lcd = ((ra+rb)/ra) v reg = (2/1)[(150/150)3.0] = 6.0v (min.)0 h (max.)f h adjustable range 5.4 6.0 [v] step voltage 40 [mv] - 26 - NJU6673 ver.2003-04-08 (3-4) lcd driving voltage generation circuits the lcd driving bias voltage of v 1 ,v 2 ,v 3 ,v 4 are generated by dividing the v 5 voltage with the internal bleeder resistance and is supplied to the lcd driving circuits after the impedence conversion by the voltage follower. the external capacitors to v 1 to v 5 for bias voltage stabilization may be removed in use of small size lcd panel. the equivalent load of lcd panel may be changed depending on display patterns. therefore, it require display quality check on various display patterns actually without external capacitors. if the display quality is not so good, external capacitors should connects as show in fig. 4. (if no need external capacitors as result of experiment, the application patterns (wiring) should be prepared for recovery.) using the internal power supply using the external power supply fig.4 reference set up value v lcd =v dd - v 5 =6.2-9.3v ? 1 short wiring or sealed wiring to the vr terminal is required due to the high impedance of vr terminal. ? 2 following connection of v out is required when external power supply using. when v ss >v 5 , v out =v 5 when v ss v 5 , v out =v ss c out to 1.0 f c 1 , c 2 to 1.0 f c3-c7 0.1 to 0.47 f r 1 1m ? r 2 500k ? r 3 1.6m ? c3 c4 c5 c6 + + + + + v 1 v 2 v 4 v 3 v 5 v out vr v5 v ss NJU6673 v dd r 1 r 2 ? 1 r 3 c7 c out c 2 - c 2 + c2 c 1 - c 1 + c1 + + + external voltage generator v 1 v 2 v 4 v 3 v 5 v out vr v 5 v ss NJU6673 v dd c 2 - c 2 + c 1 - c 1 + ? 2 . . - 27 - NJU6673 ver.2003-04-08 (4) mpu interface (4-1) interface type selection two mpu interface types are available in the NJU6673 : by 1) 8-bit bi-directional data bus (d 7 to d 0 ), 2) serial data input (si:d 7 ). the interface type (the 8 bit parallel or serial interface) is determined by the condition of the p/s terminals connecting to ?h? or ?l? level as shown in table 5. in case of the serial interface, neither the status read-out nor the ram data read-out operation is allowed.. table 5 p/s i/f type cs a0 rd wr sel68 d 7 d 6 d 5 -d 0 h parallel cs a0 rd wr sel68 d 7 d 6 d 5 -d 0 l serial cs a0 - - - si scl hi-z parallel interface the NJU6673 interfaces the 68- or 80-type mpu directly if the parallel interface (p/s=?h? is selected. the 68-type or 80-type mpu is selected by connecting the sel68 terminal to ?h? or ?l? as shown in table 6. table 6 sel68 type cs a0 rd wr d 7 -d 0 h 68 type mpu cs a0 e r/w d 7 -d 0 l 80 type mpu cs a0 rd wr d 7 -d 0 (4-2) discrimination of data bus signal the NJU6673 discriminates the mean of signal on the data bus by the combination of a0, e, r/w, and (rd, wr) signals as shown in table 7. table 7 common 68 type 80 type a0 r/w rd wr function h h l h read display data h l h l write display data l h l h status read l l h l write into the register(instruction) - 28 - NJU6673 ver.2003-04-08 (4-3) serial interface.(p/s="l") the serial interface of the NJU6673 consists of the 8-bit shift register and 3-bit counter. in case the chip is selected (cs=l), the input to d 7 (si) and d 6 (scl) becomes available, and in case that the chip isn?t selected, the shift register and the counter are reset to the initial condition. the data input from the terminal(si) is msb first like as the order of d 7 , d 6 ,------ d 0 , by a serial interface, it is entered into with rise edge of serial clock(scl). the data converted into parallel data of 8-bit with the rise edge of 8th serial clock and processed. it discriminates display data or instructions by a0 input terminal. a0 is read with rise edge of (8 x n)th of serial clock (scl), it is recognized display data by a0=?h? and instruction by a0=?l? a0 input is read in the rise edge of (8 x n)th of serial clock (scl) after chip select and distinguished. however,in case of res=?h? to ?l? or cs=?l? to ?h? with trasfered data does not fill 8 bit, attention is necessary because it will processed as there was command input. always, input the data of (8 x n) style. the scl signal must be careful of the termination reflection by the wiring length and the external noise and confirmation by the actual machine is recommended by it. fig.5 d 6 d 0 d 1 d 7 10 cs si a0 d 6 1 d 7 2 d 4 d 5 34 7 8 9 scl - 29 - NJU6673 ver.2003-04-08 (4-4) access to the display data ram and internal register. the NJU6673 transfers data to the mpu through the bus holder with the internal data bus. in case of reading out the display data contents in the dd ram, the data which was read in the first data read cycle (= the dummy read ) is memorized in the bus holder. then the data is read out to the system bus from the bus holder in the next data read cycle. also, in case that the mpu writes into dd ram, the data is temporarily stored in the bus holder and is then written into dd ram by the next data write cycle. therefore, the limitation of the access to NJU6673 from mpu side is not access time (t acc ,t ds ) of display data ram and the cycle time becomes dominant. with this, speed-up of the data transfer with the mpu becomes possible. in case of cycle time isn?t met, the mpu inserts nop operation only and becomes an equivalent to an execution of wait operation on the satisfy condition in mpu. when setting an address, the data of the specified address isn?t output immediately by the read operation after setting an address, and the data of the specified address is output at the 2nd data read operation. therefore, the dummy read is always necessary once after the address set and the write cycle. (see fig. 6) the example of read modify write operation is mentioned in (2-1)instruction -k)the sequence of inverse display. write operation read operation fig.6 (4-5) chip select cs is chip select terminal. in case of cs="l". the interface with mpu is available. in case of cs=?h?, the d 0 to d 7 are high impedance and a0, rd, wr, si and scl inputs are ignored. if the serial interface is selected when cs=?h? the shift register and counter are reset. however, the reset is always operated in any conditions of cs. i/o buffer wr wr data n n+1 n+2 n+3 n n + 1 n + 2 n + 3 i/o buffer wr n n+1 n+2 n n+1 n+2 n column address rd data read n+1 n n n n+1 address set n dummy read data read n wr data rd mpu internal timing internal timing mpu - 30 - NJU6673 ver.2003-04-08 absolute maximum ratings parameter symbol ratings unit -0.3 - +7.0 supply voltage(1) v dd -0.3 -+3.6(used tripler) v supply voltage(2) v 5 v dd -11.0 - v dd +0.3 v supply voltage(3) v 1 ,v 2 ,v 3 ,v 4 v 5 -v dd +0.3 v input voltage v in -0.3-v dd +0.3 v operating temperature t opr -30-+80 c strage temperature t stg -55-+125 c note 1) all voltage values are specified as v ss =0v. note 2) the relation of v dd > v 1 > v 2 > v 3 > v 4 > v 5 >v out ; v dd >v ss > v out must be maintained. in case of inputting external lcd driving voltage , the lcd drive voltage should start supplying to NJU6673 at the mean time of turning on v dd power supply or after turned on v dd . in use of the voltage boost circuit, the condition that the supply voltage: 11.0v> v dd -v out is necessary. note 3) if the lsi are used on condition beyond the absolute maximum rating, the lsi may be destroyed. using lsi within electrical characteristics is strongly recommended for normal operation. use beyond the erectric characteristics conditions will cause malfunction and poor reliability. note 4) decoupling capacitor should be connected between v dd and v ss due to the stabilized operation for the voltage converter. v dd v ss v 5 v dd - 31 - NJU6673 ver.2003-04-08 electrical characteristics (v dd =2.4v-3.6v, v ss =0v, ta=-20 to 75 c) parameter symbol conditions min typ max unit note recommend 2.4 3.0 3.6 operating voltage(1) available v dd 2.4 5.5 v 1 recommend v dd -10.0 v dd -4.0 available v 5 v dd -10.0 available v 1 ,v 2 v dd -0.6v lcd v dd operating voltage(2) available v 3 ,v 4 v lcd =v dd -v 5 v 5 v dd -0.4v lcd v high level v ihc 0.8v dd v dd input voltage low level v ilc a0, d 0 -d 7 , rd, wr, res, cs p/s, sel68, duty, cdir terminal v ss 0.2v dd v high level v ohc i oh =-0.5ma 0.8v dd v dd output voltage low level v olc d 0 -d 7 te r m i n a l i ol = 0.5ma v ss 0.2v dd v i li all input terminals -1.0 1.0 input leagage current i l0 d 0 to d 7 terminals, hi-z state -3.0 3.0 a driver on-resistance r on ta=25 c, v lcd =8.0v 3.0 4.5 k ? 2 stand-by current i ddq during power save mode 0.05 5.0 a 3 input terminal capacitance c in ta=25 c 10 pf 4 oscillation frequency f osc v dd = 3.0v ta =25 c 9.3 11.4 13.5 khz reset time t r res terminal 1.0 s 5 reset ?l? level pulse width t rw 10 s 6 v dd1 2.4 5.5 input voltage v dd2 3-times boost 2.4 3.3 v 7 output voltage v out1 3-times boost,v dd =3.0v -6.6 -5.5 v on-resistance r tri 3-times boost, v dd =3.0v, c out =1.0 f 1600 2600 ? a djustment range f lcd driving oltage v out2 voltage boost operation off v dd -10.0v v dd -4.0v v voltage follower v 5 voltage adjustment circuit ?off? v dd -10.0v v dd -4.0v v 8 voltage regulator v reg% v dd =3.0v; ta =25 c 3.0 % i out1 50 105 a operating current i out2 v dd =3.0v, v lcd =8v, display checkerd pattern 16 25 a 9 note 1) although the NJU6673 can operate in wide range of the operating voltage, it shall not be guaranteed in a sudden voltage fluctuation during the access with mpu. note 2) r on is the resistance values in supplying 0.1v voltage-difference beteen power supply terminals (v 1 ,v 2 ,v 3 ,v 4 ) and each output terminals (common/ segment). this is specified within the range of operating voltage(2). note 3) apply no access from mpu. note 4) apply a0, d 0 to d 7 ,rd,wr,cs,res,sel68,p/s,t 1 ,t 2 ,duty,cdir terminals. note 5) t r ( reset time ) refers to the reset completion time of the internal circuits from the rise edge of the res signal. note 6) apply minimum pulse width of the res signal. to reset, the ?l? pulse over t rw shall be input. . note 7) apply to the v dd when using 3-times boost. note 8) the voltage adjustment circuit controls v 5 within the range of the voltage follower operating voltage. voltage booster - 32 - NJU6673 ver.2003-04-08 note 9) each operating current shall be defined as being measured in the following condition. status oprating condition symbol t 1 t 2 voltage booster voltage adjustment voltage follower external voltage supply (input terminal) i out1 l l/h validity validity validity unuse i out2 h h invalidity invalidity invalidity use (v out ,v 5 ) lcd output terminal open. display on, display checered pattern, no access from mpu set v lcd =8v internal oscillator : validity measurement block diagram : i out1 : i out2 a + v dd v 5 vr 1m ? 500k ? 1.6m ? v out c 1 - c 1 + + c 2 + v ss NJU6673 c 2 - + t 1 t 2 1 NJU6673 1 0 k ? -5v c 1 - c 1 + c 2 + v ss c 2 - v dd v dd v 1 v 2 v 3 v 4 v 5 v out t 1 t 2 1 0 k ? 1 0 k ? 1 0 k ? 1 0 k ? - 33 - NJU6673 ver.2003-04-08 bus timing characteristics ? read/write operation sequence(80 type mpu) (v dd =2.4v to 3.6v, ta=-20 to 75 c) parameter symbol signal condition min typ max unit address hold time t ah8 32 address setup time t aw 8 a0, cs 0 system cycle time t cyc8 560 wr, "l" t ccl(w) 75 rd, "l" t ccl(r) 250 control pulse width "h" t cch wr, rd 275 data setup time t ds8 150 data hold time t dh8 30 rd access time t acc8 175 output disable time t oh8 d d -d 7 cl=100pf 0 44 rise time, fall time t r , t f cs,wr,rd a0, d 0 -d 7 15 ns note 1) all timing based on 20% and 80% of v dd voltage level. t cyc8 t f t r t aw 8 t ah8 t ccl t cch t ds8 t dh8 t acc8 t oh8 d 0 -d 7 (write) a0, cs wr, rd d 0 -d 7 (read) - 34 - NJU6673 ver.2003-04-08 read/write operation sequence(68 type mpu) (v dd =2.4v to 3.6v, ta=-20 to 75 c) parameter symbol signal condition min typ max unit address hold time t ah6 32 address setup time t aw 6 a0,cs r/w 32 system cycle time t cyc6 e 560 read 250 enable pulse width write t ewh e 62 data setup time t ds6 150 data hold time t dh6 50 access time t acc6 0 175 output disable time t oh6 d 0 -d 7 cl=100pf 0 56 rise time, fall time t r , t f e, r/w, a0, d 0 -d 7 15 ns note 1) all timing based on 20% and 80% of v dd voltage level. note 2) t cyc6 shows the cycle of the e signal in active cs. e t c y c6 t ewh t aw 6 t a h 6 t ds6 t dh6 t acc6 t oh6 t r t f t ewl r/w a0, cs d 0 -d 7 (write) d 0 -d 7 (read) - 35 - NJU6673 ver.2003-04-08 write operation sequence(serial interface) (v dd =2.4v-3.6v, ta=-20 to 75 c) parameter symbol signal condition min typ max unit serial clock cycle t scyc 1000 scl "h" pulse width t shw 300 scl "l" pulse width t slw scl 300 address setup time t sas 250 address hold time t sah a0 400 data setup time t sds 250 data hold time t sdh si 100 t css 60 cs-scl time t csh cs 800 rise time, fall time t f , t r cs, scl si, a0 15 ns note 1) all timing are based on 20% and 80% of v dd voltage level. cs a0 scl si t css t csh t sas t sah t scyc1 t slw t shw t f t r t sdh t sds - 36 - NJU6673 ver.2003-04-08 lcd driving waverorm v 5 v 4 v 3 v 2 v 1 v dd -v 1 -v 2 -v 3 -v 4 -v 5 -v 1 -v 2 -v 3 -v 4 -v 5 v 5 v 4 v 3 v 2 v 1 v dd c 5 c 4 c 3 c 2 c 1 c 0 c 15 c 7 c 6 c 13 c 12 c 11 c 10 c 9 c 8 c 14 s 3 s 4 s 2 s 1 s 0 fr c 1 c 0 -s 1 c 0 -s 0 s 1 s 0 v dd v 1 v 2 v 3 v 4 v 5 v dd v 1 v 2 v 3 v 4 v 5 v dd v 1 v 2 v 3 v 4 v 5 v dd v 1 v 2 v 3 v 4 v 5 c 0 c 2 v dd v 1 v 2 v 3 v 4 v 5 v dd v ss - 37 - NJU6673 ver.2003-04-08 application circuit microprocessor interface example the NJU6673 is connectable to 80-type mpu or 68-type. in use of serial interface, it is possible to be controlled by the signal line with the more small being. *:sel68 terminal shall be connected to v dd or v ss . 80 type mpu 68 type mpu serial interface reset mpu decoder NJU6673 v cc iorq d 0 -d 7 gnd a 0 a1-a7 rd wr res sel68 p/s d 0 -d 7 a 0 cs rd wr res v dd v ss v dd v dd decoder mpu NJU6673 v cc vm a gnd a 1- a 15 e r/w res a 0 d 0 -d 7 sel68 p/s d 0 -d 7 a 0 cs e r/w res v dd v ss reset v dd decoder mpu sel68 v cc gnd a 1- a 7 res a 0 port 1 port 2 NJU6673 p/s d 7 ( si ) a 0 cs res v dd v ss d 6 ( scl ) reset - 38 - NJU6673 ver.2003-04-08 memo [caution] the specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. the application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights. |
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